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We are looking for an FPGA partner to prove SARC in silicon
SARC: AI chips that run lean and stay provably exact, or safely redo the work. Never silently wrong.
Patent pending, GB2616933.4
The story
01 · The problem
The biggest way to save energy in an AI chip is the one nobody uses: just turn the power down. Every engineer knows it. And every engineer also knows what happens next. Push the voltage far enough and the arithmetic starts to wobble. Tiny mistakes. A flipped bit here, a value that comes back almost right. So the industry protects itself the only ways it can. It keeps power in reserve, running the chip well above what it truly needs, or it does the whole calculation twice and checks. Both are honest. Both work. And both quietly burn the very energy they were supposed to save. I kept thinking about how much sits in that gap.
02 · The turn
At some point we stopped asking how to avoid the errors, and asked a different question instead. What if they are not random noise at all? What if a fault has a physical shape, a signature we can measure, predict and work with, the way a sailor reads the sea instead of commanding it?
03 · The solution
That question became SARC. The chip runs lean. And when a small error shows up, SARC reconstructs the correct answer mathematically, right there, in place. Nothing is redone. And it checks itself two independent ways, so every result is either exactly right, or safely recomputed. Never silently wrong. We think that is the honest version of low-power AI.
SARC in action
Press play for the narrated walkthrough. On alternate loops, a fault cluster is too big to correct in place, so one tile takes a detour through the safe redo lane and comes back green.
Narration uses a pre-recorded natural voice. The labels carry the meaning with sound off.
The benefit, if validated
Provably correct, never silently wrong
Every result is verified and either exactly right or safely recomputed. No silent errors reach the output.
Lower energy in the compute engine
The chip runs in the low-power regime others avoid, because correctness no longer depends on generous voltage headroom.
Safety-grade integrity without duplicating the hardware
Error recovery happens mathematically, in place. No doubled silicon, no full duplicate run to compare against.
These are design goals we are now seeking to prove in hardware.
What we have achieved so far
Modelled and filed, now seeking hardware proof
Approach defined and modelled
The SARC error-recovery approach is fully defined and modelled in simulation.
Correctness mechanism validated in simulation
Validated in simulation, with near-zero undetected errors.
UK patent application filed
Patent application GB2616933.4 filed with the UK Intellectual Property Office.
FPGA hardware validation
The next step is FPGA hardware validation. That is the step we are seeking a partner for.
If it validates in silicon, this is a rare thing: real energy savings with a mathematical guarantee of correctness, in a regime the industry has always avoided. That is the result we are looking for a partner to help us prove.
The partnership
We are seeking a partner: an FPGA design lab or a university hardware group. Together we would build a small integer systolic array with our error-recovery path on an FPGA, run it first under injected faults and then under real reduced-voltage faults, and measure it against defined thresholds.
You bring the hardware bench and the FPGA toolchain. We bring the method, the models and the maths.