Compute You Can Trust, at Lower Power

Every AI system rests on a quiet assumption: that the chip underneath it does its arithmetic correctly. To keep that promise, modern accelerators run with power to spare. They hold voltage in reserve, keep comfortable margins, and in the most demanding settings duplicate their own work, all so that a calculation is never wrong. It is a sensible instinct. It is also expensive, and for a growing set of applications it is the wrong trade to accept. We built SARC to change it.

The problem with playing it safe

The single largest lever for saving energy in a chip is voltage; lower it, and the energy needed to compute falls away far faster than the voltage does. The catch is that pushing voltage down eventually makes transistors switch too slowly, and the arithmetic starts to make small mistakes. Faced with that, the industry has two familiar answers. Play it safe and keep the power, or catch a mistake and repeat the entire calculation. The first wastes the energy you were trying to save. The second is slow and costly. Both treat an error as a failure to be avoided at all costs.

A different approach

SARC takes a different view. It lets the compute run lean, in the efficient regime others avoid, and instead of fearing the occasional small error it expects it and handles it. When one appears, SARC reconstructs the correct result mathematically, in place, without redoing the work. And it does so with a guarantee that matters more than speed: every result is either exactly correct or safely recomputed. It is never quietly wrong.

Not lower energy at the cost of accuracy. Lower energy with a guarantee the answer is exact.

That guarantee is the heart of it. Undervolting to save power is not new; the reason it is not pushed harder is that it corrupts the result. SARC removes that objection. It verifies every recovered result two independent ways, so a wrong answer is never accepted. The worst case is not a silent error; it is a safe recomputation. For anything that has to be right the first time, that difference is everything.

Where it matters most

SARC is built for the places where a wrong answer is not an inconvenience but a hazard. In cars and driver-assistance systems, in robots and factory machinery, in medical devices, and in aerospace and defence, compute must be both efficient and demonstrably correct, often under tight power and thermal limits. In these settings the usual way to guarantee correctness is to duplicate the hardware, which doubles cost, power and area. SARC offers provable correctness without that duplication, which for a safety-critical design is a larger saving than efficiency alone, and a stronger foundation for certification.

Honest about where we are

We believe in saying plainly what is proven and what is not. SARC's approach rests on a physical question, how the faults of a real chip behave at a real operating point, and we are answering it the only way it can be answered, in hardware. Our modelling is encouraging and the underlying method is protected by a filed patent application, but the decisive evidence comes from silicon, and that is where our attention is now. Even in the least favourable case the guarantee holds: if the conditions are harder than expected, SARC simply recovers less often and recomputes more; it does not become wrong.

Working with us

SARC is available to explore as a licensable building block for teams designing AI silicon, from edge accelerators to safety-critical systems-on-chip. If you build compute where being correct is not optional, we would like to compare notes and, where it fits, to validate the approach against your own workloads. The goal is simple, and worth restating: compute that spends its energy wisely, lean where it can be, exact where it must be, and honest about the difference.

SARC is an approach currently moving into hardware validation; the benefits described are design goals, not measured silicon results. Patent application GB2616933.4. · Contact: Physivitis Ltd.